Device improvement by lowering LDD resistance with new silicide process

ABSTRACT

A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to semiconductor fabricationtechnology, and, more particularly, to a method of fabricating asemiconductor device such as a transistor.

[0003] 2. Description of the Related Art

[0004] There is a constant drive within the semiconductor industry toincrease the operating speed of integrated circuit devices, e.g.,microprocessors, memory devices, and the like. This drive is fueled byconsumer demands for computers and electronic devices that operate atincreasingly greater speeds. This demand for increased speed hasresulted in a continual reduction in the size of semiconductor devices,e.g., transistors. That is, many components of a typical field effecttransistor (FET), e.g., channel length, junction depths, gate dielectricthickness, and the like, are reduced. For example, all other thingsbeing equal, the smaller the channel length of the FET, the faster thetransistor will operate. Thus, there is a constant drive to reduce thesize, or scale, of the components of a typical transistor to increasethe overall speed of the transistor, as well as integrated circuitdevices incorporating such transistors. Additionally, reducing the size,or scale, of the components of a typical transistor also increases thedensity, and number, of the transistors that can be produced on a givenamount of wafer real estate, lowering the overall cost per transistor aswell as the cost of integrated circuit devices incorporating suchtransistors.

[0005] However, reducing the channel length of a transistor alsorequires reducing the size and area of electrical contacts to activeareas, such as N⁺ (P⁺) source/drain regions and a doped-polycrystallinesilicon (doped-polysilicon or doped-poly) gate conductor. As the sizeand area of the electrical contacts to the active areas get smaller, theactive area contact resistance increases. Increased active area contactresistance is undesirable for a number of reasons. For example,increased active area contact resistance may reduce device drivecurrent, and source/drain current through the device, and may alsoadversely affect the overall speed and operation of the transistor.

[0006] Typically, depositing titanium (Ti) or cobalt (Co) on the activearea electrical contacts may decrease active area contact resistance.The Ti may then be silicided by annealing with a heat-treatment to formtitanium silicide (TiSi₂) at the active area electrical contacts(self-aligned silicidation or salicidation). The salicided TiSi₂ lowersactive area contact resistance.

[0007] As shown in FIG. 1, a metal oxide semiconductor field effecttransistor (MOSFET or MOS transistor) 100 may be formed on asemiconducting substrate 105, such as doped-silicon. The MOS transistor100 may have a doped-poly gate 110 formed above a gate oxide 115 formedabove the semiconducting substrate 105. The doped-poly gate 110 and thegate oxide 115 may be separated from N⁺-doped (P⁺-doped) source/drainregions 120 of the MOS transistor 100 by dielectric spacers 125. Thedielectric spacers 125 may be formed above N⁻-doped (P⁻-doped) lightlydoped drain (LDD) regions 130.

[0008] The N⁻-doped (P⁻-doped) LDD regions 130 are typically provided toreduce the magnitude of the maximum channel electric field found closeto the N⁺-doped (P⁺-doped) source/drain regions 120 of the MOStransistor 100, and, thereby, to reduce the associated hot-carriereffects. The lower (or lighter) doping of the N⁻-doped (P⁻-doped) LDDregions 130, relative to the N⁺-doped (P⁺-doped) source/drain regions120 of the MOS transistor 100, reduces the magnitude of the maximumchannel electric field found close to the N⁺-doped (P⁺-doped)source/drain regions 120 of the MOS transistor 100, but increases thesource-to-drain resistances of the N⁻-doped (P⁻-doped) LDD regions 130.

[0009] As shown in FIG. 2, a Ti metal layer 235 may be blanket-depositedon the MOS transistor 100 shown in FIG. 1 and then subjected to aninitial rapid thermal anneal (RTA) process performed at a temperatureranging from approximately 450-800° C. for a time ranging fromapproximately 15-60 seconds. At surfaces 240 of active areas 245, suchas the N⁺-doped (P⁺-doped) source/drain regions 120 and the doped-polygate 110, exposed Si reacts upon heating with the Ti metal layer 235 toform TiSi₂ at the surfaces 240 of the active areas 245. The Ti metallayer 235 is not believed to react with the dielectric spacers 125 uponheating.

[0010] As shown in FIG. 3, a wet chemical strip of the Ti metal layer235 removes excess, unreacted portions (not shown) of the Ti metal layer235, leaving behind the salicided TiSi₂ 350 only at and below thesurfaces 240 of the active areas 245. The salicided TiSi₂ 350 may thenbe subjected to a final RTA process performed at a temperature rangingfrom approximately 800-1000° C. for a time ranging from approximately10-60 seconds.

[0011] However, even though conventional salicided TiSi₂ (or salicidedCoSi₂) lowers the contact resistances of the active areas 245, such asthe N⁺-doped (P⁺-doped) source/drain regions 120 and the doped-poly gate110, the N⁻-doped (P⁻-doped) LDD regions 130 continue to degrade thedevice drive current, and the source/drain current through the device,because of the higher resistances of the N⁻-doped (P⁻-doped) LDD regions130. The overall source-to-drain resistance, even with the conventionalsalicided TiSi₂ 350 in the N⁺-doped (P⁺-doped) source/drain regions 120,is significantly determined by the lower dopings, and, hence, higherresistances, of the N⁻-doped (P⁻-doped) LDD regions 130.

[0012] The present invention is directed to overcoming, or at leastreducing the effects of, one or more of the problems set forth above.

SUMMARY OF THE INVENTION

[0013] In one aspect of the present invention, a method is provided forfabricating a semiconductor device on a structure, the method includingforming a dielectric layer adjacent a gate conductor of thesemiconductor device and above an LDD region of the structure andremoving a first portion of the dielectric layer above the gateconductor and above the LDD region. The method also includes forming afirst conductive layer above the gate conductor, adjacent the dielectriclayer and above the LDD region and saliciding the first conductive layerabove the gate conductor and above the LDD region to form a salicidedfirst conductive layer.

[0014] In another aspect of the present invention, a semiconductordevice is provided including a structure, a gate dielectric above thestructure and a gate conductor above the gate dielectric. Thesemiconductor device also includes an LDD region of the structureadjacent the gate dielectric and the gate conductor, a dielectric layeradjacent the gate conductor and the gate dielectric, and a salicidedfirst conductive layer above the gate conductor and above the LDDregion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich the leftmost significant digit(s) in the reference numeralsdenote(s) the first figure in which the respective reference numeralsappear, and in which:

[0016] FIGS. 1-3 illustrate schematically in cross-section aconventional salicidation method for MOS transistor fabrication; and

[0017] FIGS. 4-12 illustrate schematically in cross-section variousembodiments of a method for semiconductor device fabrication accordingto the present invention.

[0018] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0019] Illustrative embodiments of the invention are described below. Inthe interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals. such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

[0020] Illustrative embodiments of a method for semiconductor devicefabrication according to the present invention are shown in FIGS. 4-12.Although the various regions and structures of a semiconductor deviceare depicted in the drawings as having very precise, sharpconfigurations and profiles, those skilled in the art recognize that, inreality, these regions and structures are not as precise as indicated inthe drawings. Nevertheless, the attached drawings are included toprovide illustrative examples of the present invention.

[0021] In general, the present invention is directed towards themanufacture of a semiconductor device. As will be readily apparent tothose skilled in the art upon a complete reading of the presentapplication, the present method is applicable to a variety oftechnologies, for example, NMOS, PMOS, CMOS, and the like, and isreadily applicable to a variety of devices, including, but not limitedto, logic devices, memory devices, and the like.

[0022] As shown in FIG. 4, a MOS transistor 400 may be formed on astructure 405 such as a semiconducting substrate (e.g., doped-silicon).The MOS transistor 400 may have a doped-poly gate 410 formed above agate dielectric 415 formed above the structure 405.

[0023] The doped-poly gate 410 may doped with arsenic (As) for an NMOStransistor for example, or boron (B) for a PMOS transistor, to renderthe poly more conductive. The poly may be formed undoped, by an LPCVDprocess for higher throughput, to have a thickness ranging fromapproximately 1000-2000 Å, for example. The doping of the poly mayconveniently be accomplished by diffusing or implanting the dopant atomsand/or molecules through the upper surface of the poly. The doped-polygate 410 may then be subjected to a heat-treating process that may be arapid thermal anneal (RTA) process performed at a temperature rangingfrom approximately 800-1100° C. for a time ranging from approximately5-60 seconds.

[0024] The gate dielectric 415 may have a thickness ranging fromapproximately 25-50 Å, for example, and may be formed from a variety ofdielectric materials and may, for example, be an oxide (e.g., Ge oxide),an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO₂), anitrogen-bearing oxide (e.g., nitrogen-bearing SiO₂), a nitrogen-dopedoxide (e.g., N₂-implanted SiO₂), silicon oxynitride (Si_(x)O_(y)N_(z)),and the like.

[0025] The gate dielectric 415 may also be formed of any suitable “highdielectric constant” or “high K” material, where K is greater than orequal to about 8, such as titanium oxide (Ti_(x)O_(y), e g, TiO₂),tantalum oxide (Ta_(x)O_(y), e.g., Ta₂O₅), barium strontium titanate(BST, BaTiO₃/SrTiO₃), and the like. The gate dielectric 415 may have anequivalent oxide thickness t_(ox-eq) ranging from approximately 25-50 Å,for example. An equivalent oxide thickness t_(ox-eq) may be defined tobe the thickness t of a dielectric material (with a dielectric constantK) that would have a capacitance C that is approximately the same as thecapacitance C_(ox) that a thickness t_(ox-eq) of silicon dioxide (SiO₂)would have. Since SiO₂ has a dielectric constant K_(ox) of approximately4, and since C=K/t and C_(ox)=K_(ox)/t_(ox-eq), thent=K/C=K/C_(ox)=Kt_(ox-eq)/K_(ox)=Kt_(ox-eq)/4, approximately. Forexample, the gate dielectric 415 may be formed of a tantalum oxide(Ta_(x)O_(y), e.g., Ta₂O₅) with a dielectric constant K_(TaO) ofapproximately 24. Then, usingt=K_(TaO)/C=K_(TaO)/C_(ox)=K_(TaO)t_(ox-eq)/K_(ox)=24t_(ox-eq)/4,approximately, an equivalent oxide thickness t_(ox-eq) ranging fromapproximately 25-50 Å would correspond to a Ta₂O₅ thickness t_(TaO)ranging from approximately 150-300 Å.

[0026] The doped-poly gate 410 and the gate dielectric 415 may beadjacent N⁻-doped (P⁻-doped) lightly doped drain (LDD) regions 420formed in the structure 405. In illustrative embodiments, the N⁻-doped(P⁻-doped) LDD regions 420 may be formed by being implanted with an LDDdose of arsenic (As, for N⁻-doping appropriate for an NMOS transistor400) or boron difluoride (BF₂, for P⁻-doping appropriate for a PMOStransistor 400). The LDD dose may range from about 1.0×10¹⁴−1.0×10¹⁵ions/cm² at an implant energy ranging from about 3-50 keV. The N⁻-doped(P⁻-doped) LDD regions 420 may be subjected to an RTA process performedat a temperature ranging from approximately 800-1100° C. for a timeranging from approximately 5-60 seconds. The RTA process may activatethe implant and form a more sharply defined and less graded activatedimplant junction with the structure 405 than would an RTA processfollowing an implant with an LDD dose of more mobile phosphorus (P, forN⁻-doping appropriate for an NMOS transistor 400) or boron (B, forP⁻-doping appropriate for a PMOS transistor 400).

[0027] As shown in FIG. 4, a dielectric layer 425 may be formed adjacentthe doped-poly gate 410 and the gate dielectric 415 of the MOStransistor 400 and above the N⁻-doped (P⁻-doped) LDD regions 420. Thedielectric layer 425 may be formed by a variety of known techniques forforming such layers, e.g., chemical vapor deposition (CVD), low-pressureCVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapordeposition (PVD), thermal growing, and the like, and may have anequivalent oxide thickness t_(ox-eq) ranging from approximately 50 Å-300Å, for example.

[0028] The dielectric layer 425 may be formed from a variety ofdielectric materials and may, for example, be an oxide (e.g., Ge oxide),an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO₂), anitrogen-bearing oxide (e.g., nitrogen-bearing SiO₂), a nitrogen-dopedoxide (e.g., N₂-implanted SiO₂), silicon oxynitride (Si_(x)O_(y)N_(z)).and the like. The dielectric layer 425 may also be formed of anysuitable “low dielectric constant” or “low K” material, where K is lessthan or equal to about 4. Alternatively, the dielectric layer 425 may beformed of any suitable “high dielectric constant” or “high K” material.where K is greater than or equal to about 8, such as titanium oxide(Ti_(x)O_(y), e g, TiO₂), tantalum oxide (Ta_(x)O_(y), e.g., Ta₂O₅),barium strontium titanate (BST, BaTiO₃/SrTiO₃), and the like. In oneillustrative embodiment, the dielectric layer 425 is comprised of asilicon dioxide (SiO₂) having a thickness of approximately 50 Å, whichis formed by being blanket-deposited by an LPCVD process for higherthroughput.

[0029] In another illustrative embodiment, the dielectric layer 425 maybe formed by, for example, thermally growing a layer of dielectricmaterial on the exposed surfaces 430 and 435 of the respectivedoped-poly gate 410 and the N⁻-doped (P⁻-doped) LDD regions 420. Notethat, in this case (not shown), the material for the dielectric layer425 would not be expected to grow thermally on the exposed sidewall 440of the gate dielectric 415. In this illustrative embodiment, thedielectric layer 425 may be comprised of SiO₂, having a thickness ofapproximately 50 Å, which is thermally grown for higher throughput. Thethermal growth may be performed in a traditional tube furnace, at atemperature ranging from approximately 700-900° C., for a time periodranging from approximately 2-10 minutes, in a nitrogen-containingambient that may include at least one of nitrous oxide (N₂O), nitricoxide (NO), ammonia (NH₃), and the like. Alternatively, the thermalgrowth may be an RTA process performed at a temperature ranging fromapproximately 700-900° C. for a time ranging from approximately 5-30seconds in a nitrogen-containing ambient that may include at least oneof nitrous oxide (N₂O), nitric oxide (NO), ammonia (NH₃), and the like.

[0030] As shown in FIG. 5, portions 525 of the dielectric layer 425remaining on the sidewalls 530 of the doped-poly gate 410 and the gatedielectric 415 of the MOS transistor 400 may be formed using a varietyof known anisotropic etching techniques, such as a reactive ion etching(RIE) process using hydrogen bromide (HBr) and argon (Ar) as the etchantgases, for example. Alternatively, an RIE process with CHF₃ and Ar asthe etchant gases may be used, for example. This anisotropic etchingremoves portions (not shown) of the dielectric layer 425 from above therespective upper surfaces 430 and 435 of the doped-poly gate 410 and theN⁻-doped (P⁻-doped) LDD regions 420 while retaining the portions 525remaining on the sidewalls 530.

[0031] As shown in FIG. 6, a first conductive layer 640 may be formedabove the respective upper surfaces 430 and 435 of the doped-poly gate410 and the N⁻-doped (P⁻-doped) LDD regions 420, and adjacent theportions 525 of the dielectric layer 425 remaining on the sidewalls 530.The first conductive layer 640 may be formed by a variety of knowntechniques, e.g., high-density ionized metal plasma (IMP) deposition,high-density inductively coupled plasma (ICP) deposition, sputtering,PVD, CVD, LPCVD, PECVD, and the like, and may have a thickness rangingfrom approximately 50-150 Å.

[0032] The first conductive layer 640 may be formed of a variety ofmaterials suitable to form a high-temperature-stable, thin silicide ableto withstand the elevated temperatures of annealing and heating, such asRTA processes used to diffuse and activate ion-implanted dopants. Suchdopant-activating RTA processes may be performed at temperatures rangingfrom approximately 800-1100° C. for a time ranging from approximately5-60 seconds.

[0033] The first conductive layer 640 may also be formed of a variety ofmaterials suitable to form a high-temperature-stable, thin silicide thatis also stable against agglomeration. Agglomeration is believed to bethe tendency of some silicides, such as titanium suicide (TiSi₂) andzirconium silicide (ZrSi₂), to try to minimize their surface areas athigh temperatures by balling up and forming spheres that increase theresistance of the agglomerated silicides. The first conductive layer 640may be formed by blanket-depositing refractory metals such as tungsten(W), molybdenum (Mo), cobalt (Co), and the like, above the respectiveupper surfaces 430 and 435 of the doped-poly gate 410 and the N⁻-doped(P⁻-doped) LDD regions 420, and adjacent the portions 525 of thedielectric layer 425 remaining on the sidewalls 530.

[0034] As shown in FIG. 7 the first conductive layer 640 may then besubjected to a self-aligned silicidation (salicidation) process torender the doped-poly gate 410 and the N⁻-doped (P⁻-doped) LDD regions420 more conductive, for example. In particular, self-aligned silicided(salicided) first conductive layers 740 are formed only at therespective upper surfaces 430 and 435 of the doped-poly gate 410 and theN⁻-doped (P⁻-doped) LDD regions 420. As shown in FIG. 7, a minimumdistance d may be provided between the salicided first conductive layers740 and a junction 745 between the N⁻-doped (P⁻-doped) LDD regions 420and the structure 405. The minimum distance d may be in a range of atleast about 50 Å-200 Å.

[0035] The first conductive layer 640 may be subjected to the first stepof a two-step heat-treating process to begin converting the firstconductive layer 640 into a metal suicide. For example, the first stepof the two-step heat-treating process may be an RTA process performed ata temperature ranging from approximately 450-800° C. for a time rangingfrom approximately 15-60 seconds. It is believed that only upperportions of the doped-poly gate 410 and the N⁻-doped (P⁻-doped) LDDregions 420 below the respective upper surfaces 430 and 435 would beconsumed to form the metal silicide of the salicided first conductivelayers 740. It is further believed that silicide will not form on theportions 525 of the dielectric layer 425 remaining on the sidewalls 530,facilitating the self-alignment of the salicidization process.

[0036] Unsilicided material in the first conductive layer 640,particularly adjacent the portions 525 of the dielectric layer 425remaining on the sidewalls 530, may be removed by a cleaning and/or awet chemical stripping, for example. Thereafter, the remaining silicidedmaterial may be subjected to the second step of the two-stepheat-treating process to finish converting the remaining portions of thefirst conductive layer 640 into the metal silicide of the salicidedfirst conductive layers 740. The salicidization process renders thedoped-poly gate 410 and the N-doped (P-doped) LDD regions 420 of thestructure 405 more conductive by providing the salicided firstconductive layers 740, lowering the overall resistivity of the MOStransistor 400.

[0037] As shown in FIG. 8, dielectric spacers 850 may be formed by avariety of techniques above the salicided first conductive layers 740above portions 855 of the N⁻-doped (P⁻-doped) LDD regions 420 andadjacent the portions 525 of the dielectric layer 425 remaining on thesidewalls 530. For example, the dielectric spacers 850 may be formed bydepositing a conformal layer of the appropriate material above andadjacent the doped-poly gate 410 and the portions 525 of the dielectriclayer 425 remaining on the sidewalls 530 and then performing ananisotropic RIE process on the conformally blanket-deposited layer. Thedielectric spacers 850 may each have a base thickness ranging fromapproximately 300-1500 Å, for example, as measured horizontally from thesidewalls 860 of the portions 525 of the dielectric layer 425 remainingon the sidewalls 530. The dielectric spacers 850, like the dielectriclayer 425, may be formed from a variety of dielectric materials and may,for example, be an oxide (e.g., Ge oxide), a nitride (e.g., GaAsnitride), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO₂),nitrogen-bearing SiO₂, silicon nitride (Si₃N₄), silicon oxynitride(Si_(x)O_(y)N_(z)), and the like. The dielectric spacers 850 may also beformed of any suitable “low dielectric constant” or “low K” material,where K is less than or equal to about 4. Additionally, the dielectricspacers 850 may be comprised of a fluorine-doped oxide, a fluorine-dopednitride, a fluorine-doped oxynitride, a fluorine-doped low K material,and the like. In one illustrative embodiment, the dielectric spacers 850are comprised of SiO₂, having a base thickness of approximately 300 Å.

[0038] In another illustrative embodiment, the dielectric spacers 850may be comprised of a material selective to the salicided firstconductive layers 740. For example, if the salicided first conductivelayers 740 were comprised of CoSi₂, then the dielectric spacers 850 maybe comprised of an oxynitride.

[0039] As shown in FIG. 9, a dopant 965 (indicated by arrows) may beimplanted to introduce dopant atoms and/or molecules to form N⁺-doped(P⁺-doped) source/drain regions 970. In one illustrative embodiment, adose of the dopant 965 atoms and/or molecules may range fromapproximately 1.0×10¹⁵-5.0×10¹⁵ ions/cm² of the appropriate dopant 965atoms and/or molecules, e.g., phosphorus (P) for an illustrative NMOStransistor or boron (B) for an illustrative PMOS transistor. An implantenergy of the dopant 965 atoms and/or molecules may range fromapproximately 30-100 keV. In another illustrative embodiment, a dose ofthe dopant 965 atoms is approximately 1.0×10¹⁵ ions/cm² of P for an NMOStransistor or B for a PMOS transistor at an implant energy ofapproximately 30 keV.

[0040] The dopant 965 may be an N⁺ implant such as phosphorus (P),arsenic (As), antimony (Sb), bismuth (Bi), and the like, and may formheavily doped N⁺ source/drain regions 970. An N⁺ implant would beappropriate for the fabrication of an NMOS transistor 400, for example.Alternatively, the dopant 965 may be a P⁺ implant such as boron (B),boron fluoride (BF, BF₂), aluminum (Al), gallium (Ga), Indium (In),Thallium (Tl), and the like, and may form heavily doped P⁺ source/drainregions 970. A P⁺ implant would be appropriate for the fabrication of aPMOS transistor 400, for example.

[0041] As shown in FIG. 10, the N⁺-doped (P⁺-doped) source/drain regions970 may be subjected to an RTA process performed at a temperatureranging from approximately 800-1100° C. for a time ranging fromapproximately 5-60 seconds. The RTA process may activate the implant ofthe more mobile P (for N⁺-doping appropriate for an NMOS transistor 400)or B (for P⁺-doping appropriate for a PMOS transistor 400) and form aless sharply defined and more graded activated implant junction 1075with the structure 405 than would an RTA process following an implantwith a source/drain dose of less mobile As (for N⁺-doping appropriatefor an NMOS transistor) or BF₂ (for P⁺-doping appropriate for a PMOStransistor).

[0042] Alternatively, an RTA process to diffuse and activate theN⁺-doped (P⁺-doped) source/drain regions 970 may be performed inconjunction with a second salicidation described in more detail below(see FIGS. 11-12), either prior to, during or following the secondsalicidation. Such a salicidation-conjoined RTA process may be performedat a temperature ranging from approximately 800-1000° C. for a timeranging from approximately 10-60 seconds.

[0043] As shown in FIG. 11, a second conductive layer 1180 may be formedabove the respective upper surfaces 430 and 435 of the salicided firstconductive layers 740 above the doped-poly gate 410 and the N⁺-doped(P⁺-doped) source/drain regions 970, and adjacent the dielectric spacers850. The second conductive layer 1180 may be formed by a variety ofknown techniques, e.g., high-density ionized metal plasma (IMP)deposition, high-density inductively coupled plasma (ICP) deposition,sputtering, PVD, CVD, LPCVD, PECVD, and the like, and may have athickness ranging from approximately 100-400 Å.

[0044] The second conductive layer 1180 may be formed of a variety ofmaterials suitable to form silicides such as titanium silicide (TiSi₂)and zirconium silicide (ZrSi₂). The second conductive layer 1180 may beformed by blanket-depositing metals such as titanium (Ti), zirconium(Zr), tungsten (W), tantalum (Ta), nickel (Ni), molybdenum (Mo), cobalt(Co), and the like, above the respective upper surfaces 430 and 435 ofthe salicided first conductive layers 740 above the doped-poly gate 410and the N⁺-doped (P⁺-doped) source/drain regions 970, and adjacent thedielectric spacers 850.

[0045] As shown in FIG. 12. the second conductive layer 1180 may then besubjected to a salicidation process to render the doped-poly gate 410and the N⁺-doped (P⁺-doped) source/drain regions 970 more conductive,for example. In particular, salicided second conductive layers 1280 areformed only at and below the respective upper surfaces 430 and 435 ofthe doped-poly gate 410 and the N⁺-doped (P⁺-doped) source/drain regions970. As shown in FIG. 12, a minimum distance D may be provided betweenthe salicided second conductive layers 1280 and a junction 1075 betweenthe N⁺-doped (P⁺-doped) source/drain regions 970 and the structure 405.The minimum distance D may be in a range of at least about 50 Å-200 Å.

[0046] The second conductive layer 1180 may be subjected to the firststep of a two-step heat-treating process to begin diffusing the metalatoms of the second conductive layer 1180 through the salicided firstconductive layers 740 and to begin converting the second conductivelayer 1180 into a metal suicide. For example, the first step of thetwo-step heat-treating process may be an RTA process performed at atemperature ranging from approximately 450-800° C. for a time rangingfrom approximately 15-60 seconds. It is believed that only upperportions of the doped-poly gate 410 and the N⁺-doped (P⁺-doped)source/drain regions 970 below the respective upper surfaces 430 and 435would be consumed to form the metal silicide of the salicided secondconductive layers 1280. It is further believed that silicide will notform on the dielectric spacers 850, facilitating the self-alignment ofthe salicidization process.

[0047] Unsilicided material in the second conductive layer 1180,particularly adjacent the dielectric spacers 850, may be removed by acleaning and/or a wet chemical stripping, for example. Thereafter, theremaining silicided material may be subjected to the second step of thetwo-step heat-treating process to finish converting the remainingportions of the second conductive layer 1180 into the metal suicide ofthe salicided second conductive layers 1280. The salicidization processrenders the doped-poly gate 410 and the N⁺-doped (P⁺-doped) source/drainregions 970 of the structure 405 more conductive by providing thesalicided second conductive layers 1280, lowering the overallresistivity of the MOS transistor 400.

[0048] Any of the above-disclosed embodiments of a method forfabricating a semiconductor device according to the present inventionprovides for increased operating speed and performance of thesemiconductor device. Additionally, the present invention allowsformation of semiconductor devices with decreased resistivity andincreased conductivity, increasing the operating speed of thesemiconductor devices and allowing more drive current.

[0049] As described above, referring to FIGS. 1-3 even thoughconventional salicided TiSi₂ (or salicided CoSi₂) lowers the contactresistances of active areas 245, such as the N⁺-doped (P⁺-doped)source/drain regions 120 and the doped-poly gate 110, the N⁻-doped(P⁻-doped) LDD regions 130 continue to degrade the device drive current,and the source/drain current through the device, because of the higherresistances of the N⁻-doped (P⁻-doped) LDD regions 130. The overallsource-to-drain resistance, even with the conventional salicided TiSi₂350 in the N⁺-doped (P⁺-doped) source/drain regions 120, issignificantly determined by the lower dopings, and, hence, higherresistances, of the N⁻-doped (P⁻-doped) LDD regions 130. By way ofcontrast any of the above-disclosed embodiments (see FIGS. 4-12) of amethod for fabricating a semiconductor device according to the presentinvention provides for lower resistances of the N⁻-doped (P⁻-doped) LDDregions 420. The overall source-to-drain resistance, even with theconventional salicided TiSi₂ 350 in the N⁺-doped (P⁺-doped) source/drainregions 970, is no longer determined by the lower dopings, and, hence,higher resistances, of the N⁻-doped (P⁻-doped) LDD regions 420 becausethe salicidization process renders the doped-poly gate 410 and theN⁻-doped (P⁻-doped) LDD regions 420 of the structure 405 more conductiveby providing the salicided first conductive layers 740, lowering theoverall source-to-drain resistance and resistivity of the MOS transistor400.

[0050] Furthermore, the above-disclosed embodiments of methods forsemiconductor device fabrication according to the present inventionenable semiconductor device fabrication with increased device densityand precision and an increased signal-to-noise ratio, and enable astreamlined and simplified process flow. For example, no additionalmasking steps are required to form both salicided source/drain regionsand salicided LDD regions in an MOS transistor and to reduce the devicechannel length. This decreases the complexity, and lowers the costs, ofthe manufacturing process, increasing reliability and throughput.

[0051] The particular embodiments disclosed above are illustrative only,as the invention may be modified and practiced in different butequivalent manners apparent to those skilled in the art having thebenefit of the teachings herein. Furthermore, no limitations areintended to the details of construction or design herein shown, otherthan as described in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

What is claimed:
 1. A method for fabricating a semiconductor device on astructure, the method comprising: forming a dielectric layer adjacent agate conductor of the semiconductor device and above an LDD region ofthe structure; removing a first portion of the dielectric layer abovethe gate conductor and above the LDD region; forming a first conductivelayer above the gate conductor, adjacent the dielectric layer and abovethe LDD region; and saliciding the first conductive layer above the gateconductor and above the LDD region to form a salicided first conductivelayer.
 2. The method of claim 1, the method further comprising: forminga dielectric spacer adjacent a second portion the dielectric layeradjacent the gate conductor; introducing a dopant into a source/drainregion of the structure; forming a second conductive layer adjacent thedielectric spacer and above the salicided first conductive layer abovethe gate conductor and above the source/drain region; and saliciding thesecond conductive layer above the gate conductor and above thesource/drain region to form a salicided second conductive layer.
 3. Themethod of claim 2, wherein forming the first conductive layer includesforming the first conductive layer from one of tungsten, molybdenum andcobalt and wherein forming the second conductive layer includes formingthe second conductive layer from one of titanium, tantalum, nickel,zirconium, tungsten, molybdenum and cobalt.
 4. The method of claim 1,wherein forming the dielectric layer includes forming the dielectriclayer from one of an oxide and an oxynitride.
 5. The method of claim 2,wherein forming the dielectric spacer includes forming the dielectricspacer from a material selective to the salicided first conductivelayer.
 6. A method for fabricating a MOSFET on a substrate, the methodcomprising: forming a dielectric layer adjacent a gate conductor of theMOSFET and above LDD regions of the substrate; removing a first portionof the dielectric layer above the gate conductor and above the LDDregions; forming a first conductive layer above the gate conductor,adjacent the dielectric layer and above the LDD regions; saliciding thefirst conductive layer above the gate conductor and above the LDDregions to form a salicided first conductive layer; forming dielectricspacers adjacent a second portion the dielectric layer adjacent the gateconductor; introducing a dopant into source/drain regions of thesubstrate; forming a second conductive layer adjacent the dielectricspacers and above the salicided first conductive layer above the gateconductor and above the source/drain regions; and saliciding the secondconductive layer above the gate conductor and above the source/drainregions to form a salicided second conductive layer.
 7. The method ofclaim 6, wherein forming the first conductive layer includes forming thefirst conductive layer from one of tungsten, molybdenum and cobalt. 8.The method of claim 6, wherein forming the second conductive layerincludes forming the second conductive layer from one of titanium,tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.
 9. Themethod of claim 6, wherein forming the dielectric layer includes formingthe dielectric layer from one of an oxide and an oxynitride.
 10. Themethod of claim
 6. wherein forming the dielectric spacers includesforming the dielectric spacers from a material selective to thesalicided first conductive layer.
 11. A method for fabricating a MOSFETon a substrate, the method comprising: depositing a dielectric layeradjacent a gate conductor and gate dielectric of the MOSFET and aboveLDD regions of the substrate; etching away a first portion of thedielectric layer above the gate conductor and above the LDD regions;depositing a first conductive layer above the gate conductor, adjacentthe dielectric layer and above the LDD regions; annealing the firstconductive layer above the gate conductor and above the LDD regions toform a salicided first conductive layer; forming dielectric spacersadjacent a second portion the dielectric layer adjacent the gateconductor and the gate dielectric; implanting a dopant into source/drainregions of the substrate; depositing a second conductive layer adjacentthe dielectric spacers and above the salicided first conductive layerabove the gate conductor and above the source/drain regions; andannealing the second conductive layer above the gate conductor and abovethe source/drain regions to form a salicided second conductive layer.12. The method of claim 11, wherein depositing the first conductivelayer includes depositing one of tungsten, molybdenum and cobalt. 13.The method of claim 11, wherein depositing the second conductive layerincludes depositing one of titanium, tantalum, nickel. zirconium,tungsten, molybdenum and cobalt.
 14. The method of claim 11, whereindepositing the dielectric layer includes depositing one of an oxide andan oxynitride.
 15. The method of claim 11, wherein forming thedielectric spacers includes forming the dielectric spacers from amaterial selective to the salicided first conductive layer.
 16. A methodfor fabricating a MOSFET on a substrate, the method comprising:depositing a dielectric layer adjacent a gate conductor and gatedielectric of the MOSFET and above LDD regions of the substrate, thedielectric layer having a thickness in a range of about 50 Å-300 Å andthe LDD regions having been implanted with an LDD dose of one of arsenicand boron difluoride and subjected to a rapid thermal anneal processperformed at a temperature ranging from approximately 800-1100° C. for atime ranging from approximately 5-60 seconds, the LDD dose ranging fromabout 1.0×10¹⁴-1.0×10¹⁵ ions/cm² at an implant energy ranging from about3-50 keV; etching away a First portion of the dielectric layer above thegate conductor and above the LDD regions using anisotropic reactive ionetching; depositing a first conductive layer above the gate conductor,adjacent the dielectric layer and above the LDD regions, the firstconductive layer having a thickness in a range of about 50 Å-150 Å;annealing the first conductive layer above the gate conductor and abovethe LDD regions to form a salicided first conductive layer, the firstconductive layer being subjected to a rapid thermal anneal processperformed at a temperature ranging from approximately 450-800° C. for atime ranging from approximately 15-60 seconds, a distance between thesalicided first conductive layer and a junction between the LDD regionsand the substrate being in a range of at least about 50 Å-200 Å; formingdielectric spacers adjacent a second portion the dielectric layeradjacent the gate conductor and the gate dielectric, the dielectricspacers having a base thickness in a range of about 300 Å-1500 Å;implanting one of phosphorus and boron into source/drain regions of thesubstrate, a dose of the one of phosphorus and boron ranging from about1.0×10¹⁵-5.0×10¹⁵ ions/cm² at an implant energy ranging from about30-100 keV; depositing a second conductive layer adjacent the dielectricspacers and above the salicided first conductive layer above the gateconductor and above the source/drain regions, the second conductivelayer having a thickness in a range of about 100 Å-400 Å; and annealingthe second conductive layer above the gate conductor and above thesource/drain regions to form a salicided second conductive layer, thesecond conductive layer being subjected to an initial rapid thermalanneal process performed at a temperature ranging from approximately450-800° C. for a time ranging from approximately 15-60 seconds, thesecond conductive layer being subjected to wet chemical strip to removeunsilicided portions of the second conductive layer, the secondconductive layer being subjected to a final rapid thermal anneal processperformed at a temperature ranging from approximately 800-1000° C. for atime ranging from approximately 10-60 seconds, a distance between thesalicided second conductive layer and a junction between thesource/drain regions and the substrate being in a range of at leastabout 50 Å-200 Å.
 17. The method of claim 16, wherein implanting the oneof phosphorus and boron into source/drain regions of the substrateincludes subjecting the source/drain regions to a rapid thermal annealprocess performed at a temperature ranging from approximately 800-1100°C. for a time ranging from approximately 5-60 seconds.
 18. The method ofclaim 16, wherein depositing the first conductive layer includesdepositing one of tungsten, molybdenum and cobalt and depositing thesecond conductive layer includes depositing one of titanium, tantalum,nickel, zirconium, tungsten, molybdenum and cobalt.
 19. The method ofclaim 16, wherein depositing the dielectric layer includes depositingone of an oxide and an oxynitride.
 20. The method of claim 16, whereindepositing the first conductive layer includes depositing cobalt andforming the dielectric spacers includes forming the dielectric spacersfrom an oxynitride.
 21. A semiconductor device comprising: a structure;a gate dielectric above the structure; a gate conductor above the gatedielectric; an LDD region of the structure adjacent the gate dielectricand the gate conductor; a dielectric layer adjacent the gate conductorand the gate dielectric; and a salicided first conductive layer abovethe gate conductor and above the LDD region.
 22. The semiconductordevice of claim 21, the semiconductor device further comprising: adielectric spacer adjacent the dielectric layer adjacent the gateconductor; a source/drain region of the structure adjacent thedielectric spacer; and a salicided second conductive layer above thegate conductor and above the source/drain region.
 23. The semiconductordevice of claim 22, wherein the first conductive layer includes one oftungsten, molybdenum and cobalt and wherein the second conductive layerincludes one of titanium, tantalum, nickel, zirconium, tungsten,molybdenum and cobalt.
 24. Thc semiconductor device of claim 21, whereinthe dielectric layer includes one of an oxide and an oxynitride.
 25. Thesemiconductor device of claim 22, wherein the dielectric spacer includesa material selective to the salicided first conductive layer.
 26. AMOSFET comprising: a substrate; a gate dielectric above the substrate; agate conductor above the gate dielectric; LDD regions of the substrateadjacent the gate dielectric and the gate conductor; a dielectric layeradjacent the gate conductor and the gate dielectric; a salicided firstconductive layer above the gate conductor and above the LDD regions;dielectric spacers adjacent the dielectric layer adjacent the gateconductor; source/drain regions of the substrate adjacent the dielectricspacers; and a salicided second conductive layer above the gateconductor and above the source/drain regions.
 27. The MOSFET of claim26, wherein the first conductive layer includes one of tungsten,molybdenum and cobalt.
 28. The MOSFET of claim
 26. wherein the secondconductive layer includes one of titanium, tantalum, nickel, zirconium,tungsten, molybdenum and cobalt.
 29. The MOSFET of claim
 26. wherein thedielectric layer includes one of an oxide and an oxynitride.
 30. TheMOSFET of claim 26, wherein the dielectric spacers include a materialselective to the salicided first conductive layer.
 31. A MOSFET on asubstrate formed by a method comprising: depositing a dielectric layeradjacent a gate conductor and gate dielectric of the MOSFET and aboveLDD regions of the substrate; etching away a first portion of thedielectric layer above the gate conductor and above the LDD regions;depositing a first conductive layer above the gate conductor, adjacentthe dielectric layer and above the LDD regions; annealing the firstconductive layer above the gate conductor and above the LDD regions toform a salicided first conductive layer; forming dielectric spacersadjacent a second portion the dielectric layer adjacent the gateconductor and the gate dielectric; implanting a dopant into source/drainregions of the substrate; depositing a second conductive layer adjacentthe dielectric spacers and above the salicided first conductive layerabove the gate conductor and above the source/drain regions; andannealing the second conductive layer above the gate conductor and abovethe source/drain regions to form a salicided second conductive layer.32. The MOSFET of claim 31, wherein depositing the first conductivelayer includes depositing one of tungsten, molybdenum and cobalt. 33.The MOSFET of claim 31, wherein depositing the second conductive layerincludes depositing one of titanium, tantalum, nickel, zirconium,tungsten, molybdenum and cobalt.
 34. The MOSFET of claim 31, whereindepositing the dielectric layer includes depositing one of an oxide andan oxynitride.
 35. The MOSFET of claim 31, wherein forming thedielectric spacers includes forming the dielectric spacers from amaterial selective to the salicided first conductive layer.
 36. A MOSFETon a substrate formed by a method comprising: depositing a dielectriclayer adjacent a gate conductor and gate dielectric of the MOSFET andabove LDD regions of the substrate, the dielectric layer having athickness in a range of about 50 Å-300 Å and the LDD regions having beenimplanted with an LDD dose of one of arsenic and boron difluoride andsubjected to a rapid thermal anneal process performed at a temperatureranging from approximately 800-1100° C. for a time ranging fromapproximately 5-60 seconds, the LDD dose ranging from about1.0×10¹⁴-1.0×10¹⁵ ions/cm² at an implant energy ranging from about 3-50keV; etching away a first portion of the dielectric layer above the gateconductor and above the LDD regions using anisotropic reactive ionetching; depositing a first conductive layer above the gate conductor,adjacent the dielectric layer and above the LDD regions. the firstconductive layer having a thickness in a range of about 50 Å-150 Å;annealing the first conductive layer above the gate conductor and abovethe LDD regions to form a salicided first conductive layer, the firstconductive layer being subjected to a rapid thermal anneal processperformed at a temperature ranging from approximately 450-800° C. for atime ranging from approximately 15-60 seconds, a distance between thesalicided first conductive layer and a junction between the LDD regionsand the substrate being in a range of at least about 50 Å-200 Å; formingdielectric spacers adjacent a second portion the dielectric layeradjacent the gate conductor and the gate dielectric, the dielectricspacers having a base thickness in a range of about 300 Å-1500 Å;implanting one of phosphorus and boron into source/drain regions of thesubstrate, a dose of the one of phosphorus and boron ranging from about1.0×10¹⁵-5.0×10¹⁵ ions/cm² at an implant energy ranging from about30-100 keV; depositing a second conductive layer adjacent the dielectricspacers and above the salicided first conductive layer above the gateconductor and above the source/drain regions, the second conductivelayer having a thickness in a range of about 100 Å-400 Å; and annealingthe second conductive layer above the gate conductor and above thesource/drain regions to form a salicided second conductive layer, thesecond conductive layer being subjected to an initial rapid thermalanneal process performed at a temperature ranging from approximately450-800° C. for a time ranging from approximately 15-60 seconds, thesecond conductive layer being subjected to wet chemical strip to removeunsilicided portions of the second conductive layer, the secondconductive layer being subjected to a final rapid thermal anneal processperformed at a temperature ranging from approximately 800-1000° C. for atime ranging from approximately 10-60 seconds, a distance between thesalicided second conductive layer and a junction between thesource/drain regions and the substrate being in a range of at leastabout 50 Å-200 Å.
 37. The MOSFET of claim 36, wherein implanting the oneof phosphorus and boron into source/drain regions of the substrateincludes subjecting the source/drain regions to a rapid thermal annealprocess performed at a temperature ranging from approximately 800-1100°C. for a time ranging from approximately 5-60 seconds.
 38. The MOSFET ofclaim 36, wherein depositing the first conductive layer includesdepositing one of tungsten, molybdenum and cobalt and depositing thesecond conductive layer includes depositing one of titanium, tantalum,nickel, zirconium, tungsten, molybdenum and cobalt.
 39. The MOSFET ofclaim 36, wherein depositing the dielectric layer includes depositingone of an oxide and an oxynitride.
 40. The MOSFET of claim 36, whereindepositing the first conductive layer includes depositing cobalt andforming the dielectric spacers includes forming the dielectric spacersfrom an oxynitride.